Enabling the Business’s First 64 Gbps UCIe IPs following the Profitable Tapeout of Alphawave Semi’s Gen2 36 Gbps UCIe IP on TSMC’s 3nm Expertise, supporting each Excessive-Yield, Low-Value Natural Substrate Commonplace Packaging (NYSE:) and Superior Packaging Applied sciences.
LONDON & TORONTO–(BUSINESS WIRE)–Alphawave Semi (LSE: AWE), a worldwide chief in high-speed connectivity and compute silicon for the world’s know-how infrastructure, proudly introduces the {industry}’s first 64 Gbps Common Chiplet Interconnect Specific (UCIe™) Die-to-Die (D2D) IP Subsystem to ship unprecedented chiplet interconnect knowledge charges, setting a brand new commonplace for ultra-high-performance D2D connectivity options within the {industry}. The third technology, 64 Gbps IP Subsystem builds on the successes of the newest Gen2 36 Gbps IP subsystem and silicon-proven Gen1 24 Gbps and is accessible in TSMC’s 3nm Expertise for each Commonplace and Superior packaging. The silicon confirmed success and tapeout milestones pave the best way for Alphawave Semi’s Gen3 UCIe™ IP subsystem providing.
Alphawave Semi is about to revolutionize connectivity with its Gen3 64 Gbps UCIe IP, delivering a bandwidth density of over 20 Tbps/mm, with ultra-low energy and latency. This resolution is extremely configurable supporting a number of protocols, together with AXI-4, AXI-S, CXS, CHI and CHI-C2C to handle the rising calls for for high-performance connectivity throughout disaggregated methods in Excessive-Efficiency Computing (HPC), Knowledge Facilities, and Synthetic Intelligence (AI) purposes.
The design complies with the most recent UCIe™ Specification and has a scalable structure with options for superior testability, together with dwell per-lane well being monitoring, making it a strong basis and enabling an open and interoperable chiplet ecosystem.
UCIe D2D interconnects facilitate a variety of ordinary and rising chiplet connectivity situations. Widespread makes use of embody linking compute chiplets for a low-latency, coherent connection by way of UCIe’s streaming capabilities, in addition to connecting compute to I/O chiplets utilizing UCIe interfaces with PCIe, CXL, or Ethernet. Moreover, optical retimers can leverage the UCIe chiplet structure to ascertain reliable, low-latency optical I/O hyperlinks by optical engines, enhancing off-system connectivity. This helps the event of low-power, high-speed options in knowledge facilities and AI/ML methods.
For top efficiency purposes, making a customized HBM base die utilizing the most recent UCIe commonplace is a cutting-edge method that entails tightly integrating reminiscence dies with compute dies to attain extraordinarily excessive bandwidth in addition to a low latency between the parts. This enables for reuse of die-to-die shoreline already occupied on the primary die for core-to-core or core-to-I/O connections. This method significantly optimizes reminiscence transactions in AI purposes the place low energy and lowered latency are efficiency differentiators.
UCIe Consortium is delighted to see members reaching crucial milestones like tapeouts, which exhibit the rising adoption of the UCIe Specification, mentioned Brian Rea, UCIe Consortium Advertising Work Group Chair. UCIe is a cornerstone of the chiplet {industry}, offering a strong resolution for high-speed, low-latency die-to-die interconnects. By embracing open requirements, we’re empowering the {industry} to speed up innovation, cut back time-to-market, and ship groundbreaking applied sciences.
“Our successful tapeout of the Gen2 UCIe™ IP at 36 Gbps on 3nm technology builds on our pioneering silicon-proven 3nm UCIe IP with CoWoS ® packaging,” mentioned Mohit Gupta, Senior VP & GM, Customized Silicon & IP, Alphawave Semi. “This achievement units the stage for our Gen3 UCIe IP at 64 Gbps, which is on track to ship excessive efficiency, 20 Tbps/mm throughput performance to our prospects who want the maximization of shoreline density for crucial AI bandwidth wants in 2025.
This achievement, alongside Alphawave Semi’s earlier industry-first 3nm silicon-proven Gen1 UCIe IP, reaffirms the corporate’s fast progress as a pacesetter in high-performance chiplet connectivity options with full suite of silicon-proven connectivity IP subsystems tailor-made for hyperscaler and data-infrastructure markets.
Study Extra:
- Uncover Alphawave Semi’s UCIe™ IP options.
- Learn our current press launch on the {industry}’s first silicon-proven 3nm UCIe™ IP.
- Discover our multi-protocol chiplet press launch.
- Watch the DAC 2024 video: From Simulation to Silicon: Alphawave & Keysight’s UCIe™ Validation.
- Learn our weblog: Redefining XPU Reminiscence for AI Knowledge Facilities By way of Customized HBM.
Click on on this hyperlink to obtain the accompanying picture.
About Alphawave Semi
Alphawave Semi is a worldwide chief in high-speed connectivity and compute silicon for the world’s know-how infrastructure. Confronted with the exponential development of information, Alphawave Semi’s know-how providers a crucial want: enabling knowledge to journey sooner, extra reliably, and with increased efficiency at decrease energy. We’re a vertically built-in semiconductor firm, and our IP, customized silicon, and connectivity merchandise are deployed by international tier-one prospects in knowledge centres, compute, networking, AI, 6G/5G, autonomous automobiles, and storage. Based in 2017 by an professional technical group with a confirmed observe report in licensing semiconductor IP, our mission is to speed up the crucial knowledge infrastructure on the coronary heart of our digital world. To seek out out extra about Alphawave Semi, go to: awavesemi.com.
Alphawave Semi and the Alphawave Semi emblem are logos of Alphawave IP Group plc. All rights reserved.
View supply model on businesswire.com: https://www.businesswire.com/information/residence/20241220920527/en/
Claudia Cano-Manuel
Grand Bridges Advertising Restricted
press@awavesemi.com
+44 7562 182327
Supply: Alphawave Semi
